Freescale Semiconductor, Inc.
Enhanced Capture Timer
BIT 7
BIt 7
Bit 7
BIt 7
Bit 7
0
6
6
6
6
6
0
5
5
5
5
5
0
4
4
4
4
4
0
3
3
3
3
3
0
2
2
2
2
2
0
1
1
1
1
1
0
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
$00B2
$00B3
$00B4
$00B5
RESET:
PA3H
PA2H
PA1H
PA0H
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
$00B2–$00B5
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see Pulse Accumulators).
BIT 7
BIt 15
Bit 7
1
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
1
BIT 0
Bit 8
Bit 0
1
$00B6
$00B7
MCCNTH
MCCNTL
RESET:
1
1
1
1
1
MCCNTH/L — Modulus Down-Counter Count Register
$00B6, $00B7
Read: any time
Write: any time
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
Advance Information
232
68HC(9)12D60 — Rev 4.0
Enhanced Capture Timer
MOTOROLA
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MOTOROLA [ MOTOROLA ]
