Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
BIT 7
PT7
I/OC7
0
6
PT6
I/OC6
0
5
PT5
I/OC5
0
4
PT4
I/OC4
0
3
PT3
I/OC3
0
2
PT2
I/OC2
0
1
PT1
I/OC1
0
BIT 0
PT0
PORT
TIMER
RESET:
I/OC0
0
PORTT — Timer Port Data Register
$00AE
Read: any time (inputs return pin level; outputs return data register
contents)
Write: data stored in an internal latch (drives pins only if configured for
output)
Since the Output Compare 7 shares the pin with Pulse Accumulator
input, the only way for Pulse accumulator to receive an independent
input from Output Compare 7 is setting both OM7 & OL7 to be zero, and
also OC7M7 in OC7M register to be zero.
OC7 is still able to reset the counter if enabled while PT7 is used as input
to Pulse Accumulator.
PORTT can be read anytime. When configured as an input, a read will
return the pin level. When configured as an output, a read will return the
latched output data.
NOTE: Writes do not change pin state when the pin is configured for timer
output. The minimum pulse width for pulse accumulator input should
always be greater than the width of two module clocks due to input
synchronizer circuitry. The minimum pulse width for the input capture
should always be greater than the width of two module clocks due to
input synchronizer circuitry.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
229
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
