Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
1 = Pulse Accumulator B system enabled. The two 8-bit pulse
accumulators PAC1 and PAC0 are cascaded to form the
PACB 16-bit pulse accumulator. When PACB in enabled, the
PACN1 and PACN0 registers contents are respectively the
high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPACR ($A8) have no
effect.
PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
PBOVI — Pulse Accumulator B Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PBOVF is set
BIT 7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
PBOVF
0
BIT 0
0
0
0
0
RESET:
PBFLG — Pulse Accumulator B Flag Register
$00B1
Read: any time
Write: any time
PBOVF — Pulse Accumulator B Overflow Flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($86) is set.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Enhanced Capture Timer
231
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