Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
MCEN — Modulus Down-Counter Enable
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
MCPR1, MCPR0 — Modulus Counter Prescaler select
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
Prescaler division
MCPR1
MCPR0
rate
0
0
1
1
0
1
0
1
1
4
8
16
BIT 7
MCZF
0
6
0
0
5
0
0
4
0
0
3
2
POLF2
0
1
BIT 0
POLF0
0
POLF3
POLF1
0
RESET:
0
MCFLG — 16-Bit Modulus Down-Counter FLAG Register
$00A7
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
The flag is set when the modulus down-counter reaches $0000.
Writing a1 to this bit clears the flag (if TFFCA=0). Writing zero has no
effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Enhanced Capture Timer
223
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MOTOROLA [ MOTOROLA ]
