Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the E÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Bits
CLK1
CLK0
Clock Source
0
0
1
0
1
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock
frequency
1
1
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator A Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
BIT 7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
PAOVF
0
BIT 0
PAIF
0
0
0
RESET:
PAFLG — Pulse Accumulator A Flag Register
$00A1
Read or write anytime. When the TFFCA bit in the TSCR register is set, any
access to the PACNT register will clear all the flags in the PAFLG register.
PAOVF — Pulse Accumulator A Overflow Flag
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Enhanced Capture Timer
219
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