Freescale Semiconductor, Inc.
Enhanced Capture Timer
MODMC — Modulus Mode Enable
0 = The counter counts once from the value written to it and will
stop at $0000.
1 = Modulus mode is enabled. When the counter reaches $0000,
the counter is loaded with the latest value written to the
modulus count register.
NOTE: For proper operation, the MCEN bit should be cleared before modifying
the MODMC bit in order to reset the modulus counter to $FF.
RDMCL — Read Modulus Down-Counter Load
0 = Reads of the modulus count register will return the present
value of the count register.
1 = Reads of the modulus count register will return the contents of
the load register.
ICLAT — Input Capture Force Latch Action
When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS ($AB) are set), a write one to this bit immediately forces the
contents of the input capture registers TC0 to TC3 and their
corresponding 8-bit pulse accumulators to be latched into the
associated holding registers. The pulse accumulators will be
automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will return always
zero.
FLMC — Force Load Register into the Modulus Counter Count Register
This bit is active only when the modulus down-counter is enabled
(MCEN=1).
A write one into this bit loads the load register into the modulus
counter count register. This also resets the modulus counter
prescaler.
Write zero to this bit has no effect.
When MODMC=0, counter starts counting and stops at $0000.
Read of this bit will return always zero.
Advance Information
222
68HC(9)12D60 — Rev 4.0
MOTOROLA
Enhanced Capture Timer
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MOTOROLA [ MOTOROLA ]
