Freescale Semiconductor, Inc.
Enhanced Capture Timer
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC0 — Timer Input Capture/Output Compare Register 0
$0090–$0091
$0092–$0093
$0094–$0095
$0096–$0097
$0098–$0099
$009A–$009B
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC1 — Timer Input Capture/Output Compare Register 1
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC2 — Timer Input Capture/Output Compare Register 2
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC3 — Timer Input Capture/Output Compare Register 3
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC4 — Timer Input Capture/Output Compare Register 4
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
Bit 0
Bit 8
Bit 0
TC5 — Timer Input Capture/Output Compare Register 5
Advance Information
68HC(9)12D60 — Rev 4.0
MOTOROLA
216
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
