Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
List of Figures
Figure
Title
Page
1-1
1-2
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
5-1
6-1
7-1
7-2
68HC(9)12D60 112-pin QFP Block Diagram . . . . . . . . . . . . . .29
68HC(9)12D60 80-pin QFP Block Diagram . . . . . . . . . . . . . . .30
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Pin Assignments in 112-pin TQFP for 68HC(9)12D60 . . . . . . .38
112-pin TQFP Mechanical Dimensions (case no987) . . . . . . .39
Pin Assignments in 80-pin QFP for 68HC(9)12D60 . . . . . . . . .40
80-pin QFP Mechanical Dimensions (case no841B) . . . . . . . .41
PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .43
Common Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . .45
External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .45
68HC(9)12D60 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .86
Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .88
Program Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Erase Sequence Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11-1 STOP Key Wake-up Filter (falling edge trigger) timing. . . . . .141
12-1 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .145
12-2 PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .150
12-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .152
12-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .155
12-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
12-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .170
12-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
12-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .172
13-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .182
13-2 Block Diagram of PWM Center-Aligned Output Channel . . . .183
13-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
14-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .199
14-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .200
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
List of Figures
19
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
