Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
List of Tables
Table
Title
Page
1-1
1-2
2-1
2-2
3-1
3-2
3-3
3-4
4-1
5-1
5-2
5-3
5-4
7-1
8-1
8-2
9-1
9-2
Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27
68HC(9)12D60 Development Tools Ordering Information . . . .28
M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .34
Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .35
68HC(9)12D60 Power and Ground Connection Summary. . . .44
68HC(9)12D60 Signal Description Summary . . . . . . . . . . . . . .51
68HC(9)12D60 Port Description Summary. . . . . . . . . . . . . . . .60
Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .61
68HC(9)12D60 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .64
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .85
EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .85
Effects of ENPE, LAT and ERAS on Array Reads . . . . . . . . .105
1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .120
Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .132
12-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .161
12-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .161
12-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
12-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .175
12-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .186
13-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . .196
13-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .196
14-1 Compare Result Output Action. . . . . . . . . . . . . . . . . . . . . . . .212
14-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .212
14-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
List of Tables
15
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MOTOROLA [ MOTOROLA ]
