Freescale Semiconductor, Inc.
List of Figures
14-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .201
14-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .202
14-5 Block Diagram for Port7 with Output compare /
Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
14-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .203
15-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .238
15-2 Serial Communications Interface Block Diagram . . . . . . . . . .239
15-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .251
15-4 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .252
15-5 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .253
15-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .254
16-1 MI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
16-2 Biphase coding and error detection . . . . . . . . . . . . . . . . . . . .266
16-3 MI BUS Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
16-4 A typical MI Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . .282
17-3 32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .286
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .286
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .287
17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .293
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
17-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . .297
17-9 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
17-10 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . .299
17-11 Receive/Transmit Message Buffer Extended Identifier. . . . . .300
17-12 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .301
18-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .324
19-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .341
19-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .341
19-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .342
20-1 V Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
FP
20-2 V Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
FP
20-3 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
20-4 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .376
20-5 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .377
20-6 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .378
20-7 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
Advance Information
20
68HC(9)12D60 — Rev 4.0
List of Figures
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
