Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
1.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
68HC(9)12D60 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . .29
1.2 Introduction
The 68HC(9)12D60 microcontroller unit (MCU) is a 16-bit device
available in two package options, 80-pin QFP and 112-pin TQFP. On-
chip peripherals include a 16-bit central processing unit (CPU12), 60K
bytes of flash EEPROM (68HC912D60) or ROM (68HC12D60), 2K
bytes of RAM, 1K bytes of EEPROM, two asynchronous serial
communication interfaces (SCI), a serial peripheral interface (SPI), an
enhanced capture timer (ECT), two (one on 80QFP) 8-channel,10-bit
analog-to-digital converters (ATD), a four-channel pulse-width
modulator (PWM), and a CAN 2.0 A, B software compatible module
(MSCAN12). System resource mapping, clock generation, interrupt
control and bus interfacing are managed by the lite integration module
(LIM). The 68HC(9)12D60 has full 16-bit data paths throughout,
however, the external bus can operate in an 8-bit narrow mode so single
8-bit wide memory can be interfaced for lower cost systems. The
inclusion of a PLL circuit allows power consumption and performance to
be adjusted to suit operational requirements. In addition to the I/O ports
available in each module, 16 (2 on 80QFP) I/O port pins are available
with Key-Wake-Up capability from STOP or WAIT mode.
68HC(9)12D60 — Rev 4.0
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Advance Information
General Description
23
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