Freescale Semiconductor, Inc.
Pulse Width Modulator
Introduction
CLOCK SOURCE
(ECLK or Scaled ECLK)
CENTR = 1
FROM PORT P
DATA REGISTER
RESET
PWCNTx
GATE
(CLOCK EDGE SYNC)
(DUTY CYCLE)
8-BIT COMPARE =
PWDTYx
T
Q
Q
MUX
MUX
(PERIOD)
8-BIT COMPARE =
PWPERx
TO PIN
DRIVER
PPOLx
PWENx
SYNC
PPOL = 1
PPOL = 0
(PWPER − PWDTY) ×2
PWDTY
PWDTY
PWPER × 2
Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
183
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com