Freescale Semiconductor, Inc.
Clock Functions
Clock Divider Chains
MCLK
TEN
REGISTER: TMSK2
BITS: PR2, PR1, PR0
0:0:0
REGISTER: MCCTL
BITS: MCPR1, MCPR0
0:0
MCEN
MODULUS
DOWN
COUNTER
0:0:1
0:1:0
0:1:1
0:1
1:0
1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 4
÷ 2
÷ 2
REGISTER: PACTL
BITS: PAEN, CLK1, CLK0
0:x:x
1:0:0
1:0:1
1:1:0
Prescaled MCLK
1:0:0
1:0:1
1:1:0
1:1:1
PULSE ACC
LOW BYTE
PACLK/256
1:1:1
PACLK/65536
(PAOV)
TO TIMER
MAIN
COUNTER
(TCNT)
PULSE ACC
HIGH BYTE
PACLK
GATE
LOGIC
PAMOD
PORT T7
PAEN
Figure 12-8. Clock Chain for ECT
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
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Clock Functions
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MOTOROLA [ MOTOROLA ]
