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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Clock Functions  
Clock Divider Chains  
BCSP BCSS  
1:x  
TCLKs  
T CLOCK  
SYSCLK  
PHASE  
LOCK  
LOOP  
PLLCLK  
TO CPU  
÷2  
GENERATOR  
ECLK  
PCLK  
E AND P  
CLOCK  
TO  
EXTALi  
EXTAL  
BUSES,  
SPI,  
PWM,  
BCSP BCSS  
0:0  
GENERATOR  
ATD0, ATD1  
REDUCED  
CONSUMPTION  
OSCILLATOR  
EXTALi  
CLKSRC = 1  
CLKSRC = 0  
BCSP BCSS  
0:1  
XTAL  
EXTALi  
TO  
MSCAN  
MCS = 0  
TO  
SCI0, SCI1,  
ECT  
MCLK  
MCS = 1  
SLOW MODE  
CLOCK  
DIVIDER  
SLWCLK  
÷ 2  
SYNC  
XCLK  
TO  
RTI, COP  
TO CAL  
CLKSW = 0  
CLKSW = 1  
÷ 2  
SYNC  
BDMCLK  
TO BDM  
TO CLOCK  
MONITOR  
Figure 12-6. Clock Generation Chain  
Bus clock select bits BCSP and BCSS in the clock select register  
(CLKSEL) determine which clock drives SYSCLK for the main system  
including the CPU and buses. BCSS has no effect if BCSP is set. During  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Advance Information  
Clock Functions  
169  
For More Information On This Product,  
Go to: www.freescale.com  
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