Freescale Semiconductor, Inc.
Clock Functions
Clock Divider Chains
BCSP BCSS
1:x
TCLKs
T CLOCK
SYSCLK
PHASE
LOCK
LOOP
PLLCLK
TO CPU
÷2
GENERATOR
ECLK
PCLK
E AND P
CLOCK
TO
EXTALi
EXTAL
BUSES,
SPI,
PWM,
BCSP BCSS
0:0
GENERATOR
ATD0, ATD1
REDUCED
CONSUMPTION
OSCILLATOR
EXTALi
CLKSRC = 1
CLKSRC = 0
BCSP BCSS
0:1
XTAL
EXTALi
TO
MSCAN
MCS = 0
TO
SCI0, SCI1,
ECT
MCLK
MCS = 1
SLOW MODE
CLOCK
DIVIDER
SLWCLK
÷ 2
SYNC
XCLK
TO
RTI, COP
TO CAL
CLKSW = 0
CLKSW = 1
÷ 2
SYNC
BDMCLK
TO BDM
TO CLOCK
MONITOR
Figure 12-6. Clock Generation Chain
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Clock Functions
169
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