Freescale Semiconductor, Inc.
Clock Functions
System Clock Frequency formulas
Bit 7
6
0
0
5
SLDV5
0
4
SLDV4
0
3
SLDV3
0
2
SLDV2
0
1
SLDV1
0
Bit 0
SLDV0
0
0
0
RESET:
SLOW — Slow mode Divider Register
$003E
Read and write anytime.
A write to this register changes the SLWCLK frequency with minimum
delay (less than one SLWCLK cycle), thus allowing immediate tune-
up of the performance versus power consumption for the modules
using this clock. The frequency divide ratio is 2 times (SLOW), hence
the divide range is 2 to 126 (not on first pass products). When
SLOW = 0, the divider is bypassed. The generation of E, P and
M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252,
by steps of 4. SLWCLK is a 50% duty cycle signal.
12.7 System Clock Frequency formulas
See Figure 12-6:
SLWCLK = EXTALi / ( 2 x SLOW )
SLWCLK = EXTALi
SLOW = 1,2,..63
SLOW = 0
PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)
ECLK = SYSCLK / 2
XCLK = SLWCLK / 2
PCLK = SYSCLK / 2
(1)
BCLK = EXTALi / 2
Boolean equations:
1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.
Advance Information
68HC(9)12D60 — Rev 4.0
MOTOROLA
Clock Functions
167
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