Freescale Semiconductor, Inc.
Clock Functions
Bit 7
6
5
AUTO
1
4
ACQ
0
3
0
0
2
PSTP
0
1
LHIE
0
Bit 0
LOCKIE
PLLON
NOLHM
(1)
(2)
RESET:
0
—
—
PLLCR — PLL Control Register
1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.
2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.
$003C
Read and write anytime. Exceptions are listed below for each bit.
LOCKIE — PLL LOCK Interrupt Enable
0 = PLL LOCK interrupt is disabled
1 = PLL LOCK interrupt is enabled
Forced to 0 when VDDPLL=0.
PLLON — Phase Lock Loop On
0 = Turns the PLL off.
1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will
lock automatically.
Cannot be cleared when BCSP = 1 (PLL selected as bus clock).
Forced to 0 when VDDPLL is at VSS level. In limp-home mode, the
output of PLLON is forced to 1, but the PLLON bit reads the latched
value.
AUTO — Automatic Bandwidth Control
0 = Automatic Mode Control is disabled and the PLL is under
software control, using ACQ bit.
1 = Automatic Mode Control is enabled. ACQ bit is read only.
Automatic bandwidth control selects either the high bandwidth
(acquisition) mode or the low bandwidth (tracking) mode depending
on how close to the desired frequency the VCO is running. See
Electrical Specifications.
Advance Information
164
68HC(9)12D60 — Rev 4.0
Clock Functions
MOTOROLA
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MOTOROLA [ MOTOROLA ]
