Freescale Semiconductor, Inc.
I/O Ports with Key Wake-up
Bit 7
WI2CE
0
6
KWIEG6
0
5
KWIEG5
0
4
KWIEG4
0
3
KWIEG3
0
2
KWIEG2
0
1
KWIEG1
0
Bit 0
KWIEG0
0
RESET:
KWIEG — Key Wake-up Port G Interrupt Enable Register
$002C
Read and write anytime.
2
WI2CE — Wake-up I C Enable
0 = PG6 default key wake-up on falling edge
2
1 = I C Start condition detection on PG7 and PG6
When WI2CE is set, PG6 and PG7 operate in wired-OR or open-drain
mode.
2
The I C Start condition is defined as a high to low transition of the
SDA line when SCL is high. When WI2CE is set, a falling edge on
PG6 (SDA) is recognized only if PG7 (SCL) is high.
2
Depending on WI2CE bit, KWIEG6 enables either falling edge or I C
Start condition interrupt.
KWIEG[6:0] — Key Wake-up Port G Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
Bit 7
KWIEH7
0
6
KWIEH6
0
5
KWIEH5
0
4
KWIEH4
0
3
KWIEH3
0
2
KWIEH2
0
1
KWIEH1
0
Bit 0
KWIEH0
0
RESET:
KWIEH — Key Wake-up Port H Interrupt Enable Register
$002D
Read and write anytime.
KWIEH[7:0] — Key Wake-up Port H Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
Advance Information
138
68HC(9)12D60 — Rev 4.0
MOTOROLA
I/O Ports with Key Wake-up
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