Freescale Semiconductor, Inc.
I/O Ports with Key Wake-up
Pull-up/down status is selected by PGUPD and PHUPD input pins: pull-
up when PxUPD pin is high, pull-down when PxUPD pin is low. On
80QFP these pins are tied internally so that KWG4 is pull-up and KWH4
is pull-down.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to Operating Modes and Resource Mapping.
11.3 Key Wake-up and Port Registers
Bit 7
PG7
—
6
5
4
3
2
1
Bit 0
PG0
—
PG6
—
PG5
—
PG4
—
PG3
—
PG2
—
PG1
—
RESET:
Alt. Pin
Function
—
KWG6
KWG5
KWG4
KWG3
KWG2
KWG1
KWG0
PORTG — Port G Register
$0028
Read and write anytime.
Bit 7
6
5
4
3
2
1
Bit 0
PH0
—
PH7
—
PH6
—
PH5
—
PH4
—
PH3
—
PH2
—
PH1
—
RESET:
Alt. Pin
Function
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
PORTH — Port H Register
$0029
Read and write anytime.
Advance Information
136
68HC(9)12D60 — Rev 4.0
MOTOROLA
I/O Ports with Key Wake-up
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MOTOROLA [ MOTOROLA ]
