Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
Section 11. I/O Ports with Key Wake-up
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
11.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .136
11.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.2 Introduction
The 112QFP 68HC(9)12D60 offers 16 additional I/O port pins with key
2
wake-up capability on 15 of them (KWG7 is used for I C start detect).
Only two (KWG4 and KWH4) are available on the 80QFP package. All
Port G and Port H pins should either be defined as outputs or have their
pull-ups/downs enabled.
The key wake-up feature of the 68HC(9)12D60 issues an interrupt that
will wake up the CPU when it is in the STOP or WAIT mode. Two ports
are associated with the key wake-up function: port G and port H. Port G
and port H wake-ups are triggered with a falling signal edge. For each
pin which has an interrupt enabled, there is a path to the interrupt
request signal which has no clocked devices when the part is in stop
mode. This allows an active edge to bring the part out of stop.
Digital filtering is included to prevent pulses shorter than a specified
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFG or KWIFH register and
its corresponding KWIEG or KWIEH bit are both set. All 15 bits/pins
share the same interrupt vector. Key wake-ups can be used with the pins
configured as inputs or outputs.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
I/O Ports with Key Wake-up
135
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