Freescale Semiconductor, Inc.
Resets and Interrupts
Register Stacking
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the address/data bus, and port E pins are normally used to
control the external bus (operation of port E pins can be affected by the
PEAR register). Out of reset, port G, port H, port P, port S, port T, port
CAN[7:2], port AD0 and port AD1 are all configured as general-purpose
inputs.
9.7.5 Central Processing Unit
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
9.7.6 Memory
After reset, the internal register block is located from $0000 to $01FF,
RAM is at $0000 to $07FF, and EEPROM is at $0C00 to $0FFF. In single
chip mode the two FLASH EEPROM(68HC912D60)/ROM(68HC12D60)
modules are located from $1000 to $7FFF and $8000 to $FFFF.
9.7.7 Other Resources
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interface (SPI), Motorola Scalable CAN (MSCAN) and
analog-to-digital converters (ATD0 and ATD1) are off after reset.
9.8 Register Stacking
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt service request is
recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Resets and Interrupts
131
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