PLL Performance Issues
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior.
There is no test that replicates these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.
4.4.1 Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and
CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges.
As defined in Figure 2-2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz
and the MF ≤ 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is
not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between
−1.4 ns and +3.2 ns.
4.4.2 Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL
and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive
load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies
greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed.
However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns.
4.4.3 Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF
(MF < 10) this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between
0.5 percent and approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent.
4.5 Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of
EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the
frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed
jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter
is less than the prescribed values.
4-5
MOTOROLA [ MOTOROLA ]
