Electrical Design Considerations
Use the following list of recommendations to ensure correct DSP operation.
• Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the
board ground to each GND pin.
• Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the
package to connect the VCC power source to GND.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND
pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer PCB with two inner layers for VCC and GND.
• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB,
IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.
• Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the VCC and GND circuits.
• All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins
with internal pull-up resistors (TRST, TMS, DE).
• Take special care to minimize noise levels on the VCCP, GND , and GNDP1 pins.
P
• The following pins must be asserted after power-up: RESET and TRST.
• If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies
due to synchronous operation of the devices.
• RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied
before deassertion of RESET.
• At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V never
CC
exceeds 3.5 V.
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MOTOROLA [ MOTOROLA ]
