5 Parallel Input/Output
The MC68HC11A8 has up to 38 input/output lines, depending on the operating mode. Port A has three
input-only pins, four output-only pins, and one bidirectional I/O pin. Port A shares functions with the tim-
er system.
Port B is an 8-bit output-only port in single-chip modes and is the high-order address in expanded
modes.
Port C is an 8-bit bidirectional port in single-chip modes and the multiplexed address and data bus in
expanded modes.
Port D is a 6-bit bidirectional port that shares functions with the serial systems.
Port E is an 8-bit input-only port that shares functions with the A/D system.
Simple and full handshake input and output functions are available on ports B and C lines in single-chip
mode. A description of the handshake functions follows.
In port B simple strobed output mode, the STRB output is pulsed for two E-clock periods each time there
is a write to the PORTB register. The INVB bit in the PIOC register controls the polarity of STRB pulses.
In port C simple strobed input mode, port C levels are latched into the alternate port C latch (PORTCL)
register on each assertion of the STRA input. STRA edge select, flag and interrupt enable bits are lo-
cated in the PIOC register. Any or all of the port C lines can still be used as general purpose I/O while
in strobed input mode.
Port C full handshake mode involves port C pins and the STRA and STRB lines. Input and output hand-
shake modes are supported, and output handshake mode has a three-stated variation. STRA is an
edge detecting input, and STRB is a handshake output. Control and enable bits are located in the PIOC
register.
In full input handshake mode, the MCU uses STRB as a “ready” line to an external system. Port C logic
levels are latched into PORTCL when the STRA line is asserted by the external system. The MCU then
negates STRB. The MCU reasserts STRB after the PORTCL register is read. A mix of latched inputs,
static inputs, and static outputs is allowed on port C, differentiated by the data direction bits and use of
the PORTC and PORTCL registers.
In full output handshake mode, the MCU writes data to PORTCL, which in turn asserts the STRB output
to indicate that data is ready. The external system reads port C (the STRB output) and asserts the STRA
input to acknowledge that data has been received.
In the three-state variation of output handshake mode, lines intended as three-state handshake outputs
are configured as inputs by clearing the corresponding DDRC bits. The MCU writes data to PORTCL
and asserts STRB. The external system responds by activating the STRA input, which forces the MCU
to drive the data in PORTCL out on all of the port C lines. This mode variation does not allow part of
port C to be used for static inputs while other port C pins are being used for handshake outputs. Refer
to the PIOC register description.
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
19
MOTOROLA [ MOTOROLA ]
