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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to IPL value. If the val-  
ues are the same, and other option register constraints are satisfied, a chip select sig-  
nal is asserted. This field only affects the response of chip selects and does not affect  
interrupt recognition by the CPU. Encoding %000 causes a chip-select signal to be as-  
serted regardless of interrupt acknowledge cycle priority, provided all other constraints  
are met.  
The AVEC bit selects one of two methods of acquiring an interrupt vector during an  
external interrupt acknowledge cycle. The internal autovector signal is generated only  
in response to interrupt requests from the SIM IRQ pins.  
4.8.1.4 PORTC Data Register  
The PORTC data register latches data for PORTC pins programmed as discrete out-  
puts. When a pin is assigned as a discrete output, the value in this register appears at  
the output. PC[6:0] correspond to CS[9:3]. Bit 7 is not used. Writing to this bit has no  
effect, and it always reads zero.  
4.8.2 Chip-Select Operation  
When the MCU makes an access, enabled chip-select circuits compare the following  
items:  
4
1. Function codes to SPACE fields, and to the IPL field if the SPACE field encod-  
ing is not for CPU32 space.  
2. Appropriate ADDR bits to base address fields.  
3. Read/write status to R/W fields.  
4. ADDR0 and/or SIZ bits to the BYTE field (16-bit ports only).  
5. Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the  
access is an interrupt acknowledge cycle).  
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same  
time as AS or DS assertion in asynchronous mode. Assertion is synchronized with  
ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field de-  
termines whether DSACK is generated internally. DSACK also determines the number  
of wait states inserted before internal DSACK assertion.  
The speed of an external device determines whether internal wait states are needed.  
Normally, wait states are inserted into the bus cycle during S3 until a peripheral as-  
serts DSACK. If a peripheral does not generate DSACK, internal DSACK generation  
must be selected and a predetermined number of wait states can be programmed into  
the chip-select option register.  
Refer to the SIM Reference Manual (SIMRM/AD) for further information.  
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge  
Ordinary I/O bus cycles use supervisor space access, but interrupt acknowledge bus  
cycles use CPU space access. Refer to 4.5.4 CPU Space Cycles for more informa-  
tion. There are no differences in flow for chip selects in each type of space, but base  
and option registers must be properly programmed for each type of external bus cycle.  
MOTOROLA  
4-54  
SYSTEM INTEGRATION MODULE  
MC68331  
USER’S MANUAL