4.6.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate re-
set lines. Reset control logic can drive four different internal signals.
1. EXTRST (external reset) drives the external reset pin.
2. CLKRST (clock reset) resets the clock module.
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU has executed
a RESET instruction.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchro-
nous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure; thus the reset
control logic responds by asserting reset to the system immediately. (A system reset,
however, caused by the CPU32 RESET instruction, is asynchronous but does not in-
dicate any type of catastrophic failure).
Synchronous resets are timed (CLKOUT) to occur at the end of bus cycles. The inter-
nal bus monitor is automatically enabled for synchronous resets. When a bus cycle
does not terminate normally, the bus monitor terminates it.
4
Refer to Table 4-15 for a summary of reset sources.
Table 4-15 Reset Source Summary
Type
Source
External
EBI
Timing
Synch
Cause
Reset Lines Asserted by Controller
External
Power Up
External Signal
MSTRST
MSTRST
CLKRST
CLKRST
EXTRST
EXTRST
Asynch
V
DD
Software Watchdog Monitor
Asynch
Asynch
Time Out
MSTRST
MSTRST
CLKRST
CLKRST
EXTRST
EXTRST
HALT
Monitor
Internal HALT Assertion
(e.g. Double Bus Fault)
Loss of Clock
Test
Clock
Test
Synch
Synch
Asynch
Loss of Reference
Test Mode
MSTRST
MSTRST
—
CLKRST
EXTRST
EXTRST
EXTRST
—
—
System
CPU32
RESET Instruction
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in Figure 4-15.
4.6.3 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 4-16 is a summary of reset mode selection options.
MC68331
SYSTEM INTEGRATION MODULE
MOTOROLA
4-37
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
