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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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Show cycles are controlled by the SHEN field in the SIMCR (refer to 4.2.3 Show In-  
ternal Cycles). This field is cleared by reset. When show cycles are disabled, the ad-  
dress bus, function codes, size, and read/write signals reflect internal bus activity, but  
AS and DS are not asserted externally and external data bus pins are in high-imped-  
ance state during internal accesses.  
When show cycles are enabled, DS is asserted externally during internal cycles, and  
internal data is driven out on the external data bus. Because internal cycles normally  
continue to run when the external bus is granted, one SHEN encoding halts internal  
bus activity while there is an external master.  
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion  
of the data bus is valid during the cycle. During a byte write to an internal address, the  
portion of the bus that represents the byte that is not written reflects internal bus con-  
ditions, and is indeterminate. During a byte write to an external address, the data mul-  
tiplexer in the SIM causes the value of the byte that is written to be driven out on both  
bytes of the data bus.  
4.6 Reset  
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.  
The RESET input is synchronized to the system clock. If there is no clock when RE-  
SET is asserted, reset does not occur until the clock starts. Resets are clocked to allow  
completion of write cycles in progress at the time RESET is asserted.  
4
Reset procedures handle system initialization and recovery from catastrophic failure.  
The MCU performs resets with a combination of hardware and software. The system  
integration module determines whether a reset is valid, asserts control signals, per-  
forms basic system configuration and boot ROM selection based on hardware mode-  
select inputs, then passes control to the CPU32.  
4.6.1 Reset Exception Processing  
The CPU32 processes resets as a type of asynchronous exception. An exception is  
an event that preempts normal processing, and can be caused by internal or external  
events. Exception processing makes the transition from normal instruction execution  
to execution of a routine that deals with an exception. Each exception has an assigned  
vector that points to an associated handler routine. These vectors are stored in the  
vector base register (VBR). The VBR contains the base address of a 1024-byte excep-  
tion vector table, which consists of 256 exception vectors. The CPU32 uses vector  
numbers to calculate displacement into the table. Refer to SECTION 5 CENTRAL  
PROCESSING UNIT for more information concerning exceptions.  
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset oc-  
curs at the end of a bus cycle, and not at an instruction boundary. Handling resets in  
this way prevents write cycles in progress at the time the reset signal is asserted from  
being corrupted. However, any processing in progress is aborted by the reset excep-  
tion, and cannot be restarted. Only essential reset tasks are performed during excep-  
tion processing. Other initialization tasks must be accomplished by the exception  
handler routine. 4.6.8 Reset Processing Summary contains details of exception pro-  
cessing.  
MOTOROLA  
4-36  
SYSTEM INTEGRATION MODULE  
MC68331  
USER’S MANUAL