Y[5:0] — Frequency Control (Counter)
The Y field is the initial value for the modulus 64 down counter in the synthesizer feed-
back loop. Values range from 0 to 63.
EDIV — ECLK Divide Rate
0 = ECLK is system clock divided by 8
1 = ECLK is system clock divided by 16
SLIMP — Limp Mode
0 = External crystal is VCO reference
1 = Loss of crystal reference
SLOCK — Synthesizer Lock
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or system clock is external.
RSTEN — Reset Enable
0 = Loss of reference causes the MCU to operate in limp mode.
1 = Loss of reference causes system reset.
STSIM — Stop Mode System Integration Clock
D
0 = SIM clock driven by an external source and VCO off during low-power stop.
1 = SIM clock driven by VCO during low-power stop.
STEXT — Stop Mode External Clock
0 = CLKOUT held low during low-power stop.
1 = CLKOUT driven from SIM clock during low-power stop.
D.3.4 RSR — Reset Status Register
$YFFA07
15
8
7
6
5
4
3
0
2
1
0
NOT USED
EXT
POW
SW
HLT
LOC
SYS
TST
RSR contains a status bit for each reset source in the MCU. RSR is updated when the
MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple
sources assert reset signals at the same time, more than one bit in RSR may be set.
This register can be read at any time; a write has no effect.
EXT — External Reset
Reset caused by an external signal.
POW — Power-Up Reset
Reset caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset caused by the halt monitor.
MOTOROLA
D-16
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
