LOC — Loss of Clock Reset
Reset caused by loss of clock frequency reference.
SYS — System Reset
Reset caused by a RESET instruction.
TST — Test Submodule Reset
Reset caused by the test submodule. Used during system test only.
D.3.5 SIMTRE — System Integration Test Register (ECLK)
$YFFA08
Register is used for factory test only.
D.3.6 PORTE0/PORTE1 — Port E Data Register
$YFFA11, $YFFA13
15
8
7
6
5
4
3
2
1
0
NOT USED
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
U
U
U
U
U
U
U
U
D
PORTE is an internal data latch that can be accessed at two locations. PORTE can be
read or written at any time. If a pin in I/O port E is configured as an output, the corre-
sponding bit value is driven out on the pin. When a pin is configured for output, a read
of PORTE returns the latched bit value; when a pin is configured for input, a read re-
turns the pin logic level.
D.3.7 DDRE — Port E Data Direction Register
$YFFA15
15
8
7
6
5
4
3
2
1
0
NOT USED
DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
RESET:
0
0
0
0
0
0
0
0
Bits in this register control the direction of the port E pin drivers when pins are config-
ured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit
configures the corresponding pin as an input. This register can be read or written at
any time.
D.3.8 PEPAR — Port E Pin Assignment Register
$YFFA17
15
8
7
6
5
4
3
2
1
0
NOT USED
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
RESET:
DATA8
DATA8
DATA8
DATA8
DATA8
DATA8
DATA8
DATA8
Bits in this register determine the function of port E pins. Setting a bit assigns the cor-
responding pin to a bus control signal; clearing a bit assigns the pin to I/O port E.
MC68331
REGISTER SUMMARY
MOTOROLA
D-17
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
