F1B — Force Logic Level One on PWMB
0 = Force logic level zero output on PWMB pin.
1 = Force logic level one output on PWMB pin.
D.2.15 PWMA/PWMB — PWM Registers A/B
$YFF926, $YFF927
The value in these registers determines pulse width of the corresponding PWM output.
A value of $00 corresponds to continuously low output; a value of $80 to 50% duty cy-
cle. Maximum value ($FF) selects an output that is high for 255/256 of the period.
Writes to these registers are buffered by PWMBUFA and PWMBUFB.
D.2.16 PWMCNT — PWM Count Register
$YFF928
PWMCNT is the 16-bit free-running counter used for GPT PWM functions.
D.2.17 PWMBUFA — PWM Buffer Register A
PWMBUFB — PWM Buffer Register B
$YFF92A
$YFF92B
To prevent glitches when PWM duty cycle is changed, the contents of PWMA and
PWMB are transferred to these read-only registers at the end of each duty cycle. Re-
set state is $0000.
D
D.2.18 PRESCL — GPT Prescaler
$YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always
read as zeros. Reset state is $0000.
MOTOROLA
D-12
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
