FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer
operations.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the
user or supervisor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor
access only.
MM — Module Mapping
D
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Determines SIM interrupt arbitration priority. The reset value is $F (highest priority), to
prevent SIM interrupts from being discarded during initialization.
D.3.2 SIMTR — System Integration Test Register
$YFFA02
SIMTR is used for factory test only.
D.3.3 SYNCR — Clock Synthesizer Control Register
$YFFA04
15
W
14
X
13
8
7
6
0
5
0
4
3
2
1
0
Y
EDIV
SLIMP
SLOCK
RSTEN
STSIM
STEXT
RESET:
0
0
1
1
1
1
1
1
0
0
0
U
U
0
0
0
SYNCR determines system clock operating frequency and mode of operation.
Clock frequency is determined by SYNCR bit settings as follows:
.
W — Frequency Control (VCO)
0 = Base VCO frequency
1 = VCO frequency multiplied by four
X — Frequency Control Bit (Prescale)
0 = VCO frequency divided by four (base system clock frequency)
1 = VCO frequency divided by two (system clock frequency doubles)
MC68331
REGISTER SUMMARY
MOTOROLA
D-15
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
