7.4.2 GPT Interrupts
The GPT has 11 internal sources that can cause it to request interrupt service (refer
to Table 7-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources.
TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one
16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and
TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position.
TMSK2 also controls the operation of the timer prescaler. Refer to 7.7 Prescaler for
more information.
The value of the interrupt level (IRL) field in the interrupt control register (ICR) deter-
mines the priority of GPT interrupt requests. IRL values correspond to MCU interrupt
request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request signal; IRQ1 is
the lowest-priority signal. A value of %111 causes IRQ7 to be asserted when a GPT
interrupt request is made; lower field values cause corresponding lower-priority inter-
rupt request signals to be asserted. Setting field value to %000 disables interrupts.
Table 7-2 GPT Interrupt Sources
Name
Source
Number
Source
Vector
Number
—
IC1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Adjusted Channel
Input Capture 1
IVBA : 0000
IVBA : 0001
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
7
IC2
Input Capture 2
IC3
Input Capture 3
OC1
OC2
OC3
OC4
IC4/OC5
TO
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow
PAOV
PAI
Pulse Accumulator Overflow
Pulse Accumulator Input
The CPU32 recognizes only interrupt request signals of a priority greater than the sta-
tus register interrupt priority (IP) mask value. When the CPU acknowledges an inter-
rupt request, the priority of the acknowledged request is written to the IP mask and
driven out on the IMB address lines.
When the IP mask value driven out on the address lines is the same as the IRL value,
the GPT contends for arbitration priority. GPT arbitration priority is determined by the
value of the IARB field in GPTMCR. Each MCU module that can make interrupt re-
quests must be assigned a nonzero IARB value in order to implement an arbitration
scheme. Arbitration is performed by means of serial assertion of IARB field bit values.
When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge
cycle by placing an interrupt vector number on the data bus. The vector number is
used to calculate displacement into the CPU32 exception vector table. Vector num-
bers are formed by concatenating the value in the ICR IVBA field with a 4-bit value
supplied by the GPT when an interrupt request is made. Hardware prevents the vector
number from changing while it is being driven out on the IMB. Vector number assign-
ment is shown in Table 7-2.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-5
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
