7.3 Special Modes of Operation
The GPT module configuration register (GPTMCR) module configuration register
(GPTMCR) is used to control special GPT operating modes. These include low-power
stop mode, freeze mode, single-step mode, and test mode. Normal GPT operation can
be polled or interrupt-driven. Refer to 7.4 Polled and Interrupt-Driven Operation for
more information.
7.3.1 Low-Power Stop Mode
Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop
mode the system clock to the module is turned off. The clock remains off until STOP
is negated or a reset occurs. All counters and prescalers within the timer stop counting
while the STOP bit is set. Only the module configuration register (GPTMCR) and the
interrupt configuration register (ICR) should be accessed while in the stop mode. Ac-
cesses to other GPT registers cause unpredictable behavior. Low-power stop can also
be used to disable module operation during debugging.
7.3.2 Freeze Mode
The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by
the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ1 has no effect;
setting FRZ0 causes the GPT to enter freeze mode. Refer to SECTION 5 CENTRAL
PROCESSING UNIT for more information on background debugging mode.
7
Freeze mode freezes the current state of the timer. The prescaler and the pulse accu-
mulator do not increment and changes to the pins are ignored (input pin synchronizers
are not clocked). All of the other timer functions that are controlled by the CPU will op-
erate normally; for example, registers can be written to change pin directions, force
output compares, and read or write I/O pins.
While the FREEZE signal is asserted, the CPU has write access to registers and bits
that are normally read-only, or write-once. The write-once bits can be written to as of-
ten as needed. The prescaler and the pulse accumulator remain stopped and the input
pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM),
the FRZ0 bit is cleared, or the MCU is reset.
Activities that are in progress prior to FREEZE assertion are completed. For example,
if an input edge on an input capture pin is detected just as the FREEZE signal is as-
serted, the capture occurs and the corresponding interrupt flag is set.
7.3.3 Single-Step Mode
Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP
bit is asserted, the prescaler and the pulse accumulator stop counting and changes at
input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP
was set. After STOPP is set, the INCP bit can be set to increment the prescaler and
clock the input synchronizers once. The INCP bit is self-negating after the prescaler is
incremented. INCP can be set repeatedly. The INCP bit has no effect when the
STOPP bit is not set.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-3
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
