be used to output the clock selected for the timer counter register. Any of these pins
can also be used for general-purpose I/O. Refer to 7.8.3 Output Compare Functions
for more information.
7.5.4 Pulse Accumulator Input Pin (PAI)
The PAI pin connects a discrete signal to the pulse accumulator for timed or gated
pulse accumulation. PAI has hysteresis. Any pulse longer than two system clocks is
guaranteed to be valid and any pulse shorter than one system clock is ignored. It can
be used as a general-purpose input pin. Refer to 7.10 Pulse Accumulator for more
information.
7.5.5 Pulse-Width Modulation (PWMA, PWMB)
PWMA and PWMB pins carry pulse-width modulator outputs. The modulators can be
programmed to generate a periodic waveform of variable frequency and duty cycle.
PWMA can be used to output the clock selected as the input to the PWM counter.
These pins can also be used for general-purpose output. Refer to 7.11 Pulse-Width
Modulation Unit for more information.
7
7.5.6 Auxiliary Timer Clock Input (PCLK)
PCLK connects an external clock to the GPT. The external clock can be used as the
clock source for the capture/compare unit or the PWM unit in place of one of the pres-
caler outputs. PCLK has hysteresis. Any pulse longer than two system clocks is guar-
anteed to be valid and any pulse shorter than one system clock is ignored. This pin
can also be used as a general-purpose input pin. Refer to 7.7 Prescaler for more in-
formation.
7.6 General-Purpose I/O
Any GPT pin can be used for general-purpose I/O when it is not used for another pur-
pose. Capture/compare pins are bidirectional, others can be used only for output or
input. I/O direction is controlled by a data direction bit in the port GP data direction reg-
ister (DDRGP).
Parallel data is read from and written to the port GP data register (PORTGP). Pin data
can be read even when pins are configured for a timer function. Data read from PORT-
GP always reflects the state of the external pin, while data written to PORTGP may
not always affect the external pin.
Data written to PORTGP does not immediately affect pins used for output compare
functions, but the data is latched. When an output compare function is disabled, the
last data written to PORTGP is driven out on the associated pin if it is configured as
an output. Data written to PORTGP can cause input captures if the corresponding pin
is configured for input capture function.
The pulse accumulator input (PAI and the external clock input (PCLK) pins provide
general-purpose input. The state of these pins can be read by accessing the PAIS and
PCLKS bits in the pulse accumulator control register (PACTL).
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-7
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
