OC1/PGP3
IC1/PGP0
IC2/PGP1
IC3/PGP2
OC2/OC1/PGP4
OC3/OC1/PGP5
OC4/OC1/PGP6
IC4/OC5/OC1/PGP7
CAPTURE/COMPARE UNIT
PULSE ACCUMULATOR
PRESCALER
PAI
PCLK
PWMA
PWMB
PWM UNIT
BUS INTERFACE
IMB
7
GPT BLOCK
Figure 7-1 GPT Block Diagram
7.2 GPT Registers and Address Map
The GPT programming model consists of a configuration register (GPTMCR), parallel
I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2,
TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL),
pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,
PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1,
TMSK2). Functions of the module configuration register are discussed in 7.3 Special
Modes of Operation and 7.4 Polled and Interrupt-Driven Operation. Other register
functions are discussed in the appropriate sections.
All registers can be accessed using byte or word operations. Certain capture/compare
registers and pulse-width modulation registers must be accessed by word operations
to ensure coherency. If byte accesses are used to read a register such as the timer
counter register (TCNT), there is a possibility that data in the byte not being accessed
will change while the other byte is read. Both bytes must be accessed at the same
time.
The modmap (MM) bit in the system integration module configuration register (SIM-
CR) defines the most significant bit (ADDR23) of the IMB address for each register in
the MCU.
Refer to APPENDIX D REGISTER SUMMARY for a GPT address map and register
bit/field descriptions. SECTION 4 SYSTEM INTEGRATION MODULE contains more
information about how the state of MM affects the system.
MOTOROLA
7-2
GENERAL-PURPOSE TIMER
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
