SYSTEM CLOCK
DIVIDER
÷512
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
EXT.
CPR2 CPR1 CPR0
÷256
÷128
÷64
÷32
÷16
÷8
TO CAPTURE/
COMPARE
TIMER
SELECT
÷4
EXT.
7
÷128
÷64
÷32
÷16
÷8
TO
PWM UNIT
SELECT
÷4
÷2
EXT.
PCLK
PIN
SYNCHRONIZER AND
DIGITAL FILTER
GPT PRESCALER BLOCK
PPR2 PPR1 PPR0
Figure 7-2 Prescaler Block Diagram
Multiplexer outputs (including the PCLK signal) can be connected to external pins) can
be connected to external pins. The CPROUT bit in the TMSK2 register configures the
OC1 pin to output the TCNT clock and the PPROUT bit in the PWMC register config-
ures the PWMA pin to output the PWMC clock. CPROUT and PPROUT can be written
at any time. Clock signals on OC1 and PWMA do not have a 50% duty cycle. They
have the period of the selected clock but are high for only one system clock time.
The prescaler also supplies three clock signals to the pulse accumulator clock select
mux. These are the system clock divided by 512, the external clock signal from the
PCLK pin and the capture/compare clock signal.
7.8 Capture/Compare Unit
The capture/compare unit contains the timer counter (TCNT), the input capture (IC)
functions and the output compare (OC) functions. Figure 7-3 is a block diagram of the
capture/compare unit.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-9
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
