lows idle time between frames and eliminates idle time between transmissions. How-
ever, there is a loss of efficiency because of an additional bit-time per frame.
6.4.3.9 Internal Loop
The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When
LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. TXD is
asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
6.5 QSM Initialization
After reset, the QSM remains in an idle state until initialized. A general sequence guide
for initialization follows.
A. Global
1. Configuration register (QSMCR)
a. Write an interrupt arbitration priority value into the IARB field.
b. Clear the FREEZE and/or STOP bits for normal operation.
2. Interrupt vector and interrupt level registers (QIVR and QILR)
a. Write QSPI/SCI interrupt vector into QIVR.
b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
3. Port data and data direction registers (PORTQS and DDRQS)
a. Write a data word to PORTQS.
6
b. Establish direction of QSM pins used for I/O by writing to DDRQS.
4. Assign pin functions by writing to the pin assignment register (PQSPAR)
B. Queued Serial Peripheral Interface
1. Write appropriate values to QSPI command RAM.
2. QSPI control register zero (SPCR0)
a. Write a transfer rate value into the BR field.
b. Determine clock phase (CPHA), and clock polarity (CPOL).
c. Determine number of bits to be transferred in a serial operation (BIT).
d. Select master or slave operating mode (MSTR).
e. Enable or disable wired-OR operation (WOMQ).
3. QSPI control register one (SPCR1)
a. Establish a delay following serial transfer by writing to the DTL field.
b. Establish a delay before serial transfer by writing to the DSCKL field.
4. QSPI control register two (SPCR2)
a. Write an initial queue pointer value into the NEWQP field.
b. Write a final queue pointer value into the ENDQP field.
c. Enable or disable queue wraparound (WREN).
d. Write wraparound address into the WRTO field.
e. Enable or disable QSPI flag interrupt (SPIFIE).
5. QSPI control register three (SPCR3)
a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE).
c. Enable or disable loopback (LOOPQ).
6. To enable the QSPI, set the SPE bit in SPCR1.
MC68331
QUEUED SERIAL MODULE
MOTOROLA
6-31
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
