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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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5.2.3 Program Counter  
The PC contains the address of the next instruction to be executed by the CPU32. Dur-  
ing instruction execution and exception processing, the processor automatically incre-  
ments the contents of the PC or places a new value in the PC as appropriate.  
5.2.4 Control Registers  
The control registers described in this section contain control information for supervi-  
sor functions and vary in size. With the exception of the condition code register (the  
user portion of the status register), they are accessed only by instructions at the su-  
pervisor privilege level.  
5.2.4.1 Status Register  
The status register (SR) stores the processor status. It contains the condition codes  
that reflect the results of a previous operation and can be used for conditional instruc-  
tion execution in a program. The condition codes are extend (X), negative (N), zero  
(Z), overflow (V), and carry (C). The user (low-order) byte containing the condition  
codes is the only portion of the SR information available at the user privilege level; it  
is referenced as the condition code register (CCR) in user programs.  
5
At the supervisor privilege level, software can access the full status register. The upper  
byte of this register includes the interrupt priority (IP) mask (three bits), two bits for  
placing the processor in one of two tracing modes or disabling tracing, and the super-  
visor/user bit for placing the processor at the desired privilege level.  
Undefined bits in the status register are reserved by Motorola for future definition. The  
undefined bits are read as zeros and should be written as zeros for future compatibility.  
All operations to the SR and CCR are word-size operations, but for all CCR operations,  
the upper byte is read as all zeros and is ignored when written, regardless of privilege  
level.  
Refer to APPENDIX D REGISTER SUMMARY for bit/field definitions and a diagram  
of the status register.  
5.2.4.2 Alternate Function Code Registers  
Alternate function code registers (SFC and DFC) contain 3-bit function codes. Func-  
tion codes can be considered extensions of the 24-bit linear address that optionally  
provide as many as eight 16-Mbyte address spaces. The processor automatically gen-  
erates function codes to select address spaces for data and programs at the user and  
supervisor privilege levels and to select a CPU address space used for processor  
functions (such as breakpoint and interrupt acknowledge cycles).  
Registers SFC and DFC are used by the MOVES instruction to specify explicitly the  
function codes of the memory address. The MOVEC instruction is used to transfer val-  
ues to and from the alternate function code registers. This is a long-word transfer; the  
upper 29 bits are read as zeros and are ignored when written.  
MOTOROLA  
5-6  
CENTRAL PROCESSING UNIT  
MC68331  
USER’S MANUAL