MC145157–2 BLOCK DIAGRAM
14–BIT SHIFT REGISTER
14
f
R
ENB
REFERENCE COUNTER LATCH
14
LOCK
DETECT
LD
PD
OSC
14–BIT
÷
R COUNTER
in
out
out
PHASE
DETECTOR
A
OSC
REF
out
PHASE
DETECTOR
B
φ
V
14–BIT
÷
N COUNTER
14
f
in
φ
R
÷
N COUNTER LATCH
14
f
V
1–BIT
CONTROL
S/R
DATA
CLK
S/R
out
14–BIT SHIFT REGISTER
if the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed
high to transfer data to the latches.
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 8)
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 1, 2)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ N counter. This input has an
inverter biased in the linear region to allow use with ac
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), dc coupling may be
used.
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
ated reference signal. This signal is typically ac coupled to
CLK, DATA
OSC , but for larger amplitude signals (standard CMOS
in
Shift Clock, Serial Data Inputs (Pins 9, 10)
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
.
Each low–to–high transition of the clock shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷ N counter latch. The entry format is as follows:
out
OUTPUT PINS
PD
out
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency f > f or f Leading: Negative Pulses
V
R
V
Frequency f < f or f Lagging: Positive Pulses
V
R
V
FIRST DATA BIT INTO SHIFT REGISTER
Frequency f = f and Phase Coincidence: High–Imped-
V
R
ance State
ENB
Latch Enable Input (Pin 11)
φ , φ
R
V
Double–Ended Phase Detector B Outputs (Pins 16, 15)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or ÷ N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N latches are activated
These outputs can be combined externally for a loop–error
signal. A single–ended output is also available for this pur-
pose (see PD
).
out
MC145151–2 through MC145158–2
18
MOTOROLA
MOTOROLA [ MOTOROLA ]
