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V58C2128804S 参数 Datasheet PDF下载

V58C2128804S图片预览
型号: V58C2128804S
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能2.5伏128兆位的DDR SDRAM [HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 59 页 / 922 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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V58C2128(804/404/164)S  
TRUTH TABLE 2 – CKE  
(Notes: 1-4)  
CKEn-1 CKEn  
CURRENT STATE  
COMMANDn  
ACTIONn  
Maintain Power-Down  
Maintain Self Refresh  
NOTES  
Power-Down  
Self Refresh  
X
X
L
L
Power-Down  
Self Refresh  
DESELECT or NOP  
DESELECT or NOP  
Exit Power-Down  
Exit Self Refresh  
L
H
5
All Banks Idle  
Bank(s) Active  
All Banks Idle  
DESELECT or NOP  
DESELECT or NOP  
AUTO REFRESH  
See Truth Table 3  
Precharge Power-Down Entry  
Active Power-Down Entry  
Self Refresh Entry  
H
L
H
H
NOTE:  
1. CKE is the logic state of CKE at clock edge n; CKE was the state of CKE at the previous clock edge.  
n
n-1  
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.  
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.  
4. All states and sequences not shown are illegal or reserved.  
t
5. DESELECT or NOP commands should be issued on any clock edges occurring during the XSR period.  
A minimum of 200 clock cycles is needed before applying a read command, for the DLL to lock.  
V58C2128(804/404/164)S Rev. 1.6 March 2002  
27  
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