V436516Y04V
AC Characteristics
T = 0° to 70°C; V = 0V; V = 3.3V ± 0.3V, t = 1 ns (Continued)
A
SS
CC
T
Limit Values
-75
-75PC
-10PC
#
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
Read Cycle
21
22
23
24
tOH
Data Out Hold Time
2.7
1
–
–
2.7
1
–
–
2.7
1
–
–
ns
ns
2
7
tLZ
tHZ
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
–
5.4
2
–
5.4
2
–
5.4
2
ns
tDQZ
–
–
–
CLK
Write Cycle
25
26
tWR
tDQW
Write Recovery Time
1
0
–
–
1
0
–
–
1
0
–
–
CLK
CLK
DQM Write Mask Latency
Notes:
1. The specified values are valid when addresses are changed no more than once during t (min.) and when No
CK
Operation commands are registered on every rising clock edge during t (min). Values are shown per module
RC
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t (min.).
RC
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V = 0.4V and V = 2.4V with the timing referenced to the 1.4V crossover point. The transition
IL
IH
time is measured between V and V . All AC measurements assume t = 1 ns with the AC output load circuit
IH
IL
T
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
0.4V
50 Ohm
CLOCK
tCL
Z=50 Ohm
tT
I/O
tSETUP tHOLD
50 pF
1.4V
INPUT
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
V436516Y04V Rev. 1.0 October 2001
8
MOSEL [ MOSEL VITELIC, CORP ]
