V436516Y04V
SPD-Table for -75 modules: (Continued)
Hex Value
Byte
133 MHz
-75PC
133 MHZ
-75
100 MHZ
-10PC
Number Function Described
SPD Entry Value
42 ns/45 ns
30
31
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
2A
10
15
08
15
08
00
02
D2
00
2D
10
15
08
15
08
00
02
17
00
2D
10
20
10
20
10
00
12
84
00
64 MByte
32
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
35
36-61
62
Revision 2/1.2
63
Checksum for Bytes 0 - 62
64-125 Manufacturers’s Information (Optional)
126
127
Max. Frequency Specification
Frequency Support Details
Unused Storage Location
133 MHz
64
00
64
00
64
00
128+
Absolute Maximum Ratings
Parameter
Max.
-1 to 4.6
-1 to 4.6
0 to +70
-55 to 125
3.5
Units
V
Voltage on VDD Supply Relative to VSS
Voltage on Input Relative to VSS
Operating Temperature
Storage Temperature
V
°C
°C
W
Power Dissipation
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
A
SS
DD
DDQ
Limit Values
Symbol Parameter
Min.
2.0
Max.
VCC+0.3
0.8
Unit
V
VIH
VIL
Input High Voltage
Input Low Voltage
–0.5
2.4
V
VOH
VOL
II(L)
Output High Voltage (IOUT = –2.0 mA)
Output Low Voltage (IOUT = 2.0 mA)
Input Leakage Current, any input
—
V
—
0.4
V
–10
10
µA
(0 V < VIN < 3.6 V, all other inputs = 0V)
IO(L)
Output leakage current
–10
10
µA
(DQ is disabled, 0V < VOUT < VCC
)
V436516Y04V Rev. 1.0 October 2001
5
MOSEL [ MOSEL VITELIC, CORP ]
