V436516Y04V
Serial Presence Detect Information
2
A serial presence detect storage device –
written into the E PROM device during module pro-
2
2
E PROM – is assembled onto the module. Informa-
duction using a serial presence detect protocol (I C
tion about the module configuration, speed, etc. is
synchronous 2-wire bus)
SPD-Table for -75 modules:
Hex Value
Byte
133 MHz
-75PC
133 MHZ
-75
100 MHZ
-10PC
Number Function Described
SPD Entry Value
0
1
Number of SPD bytes
128
80
08
04
0C
09
02
40
00
01
75
54
00
80
10
00
01
80
08
04
0C
09
02
40
00
01
75
54
00
80
10
00
01
80
08
04
0C
09
02
40
00
01
A0
60
00
80
10
00
01
Total bytes in Serial PD
256
2
Memory Type
SDRAM
3
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x16 SDRAM)
Number of DIMM Banks
12
4
9
5
2
6
Module Data Width
64
0
7
Module Data Width (continued)
Module Interface Levels
8
LVTTL
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns/10.0 ns
5.4 ns/6.0 ns
none
10
11
12
13
14
15
Self-Refresh, 15.6µs
x16
SDRAM width, Primary
Error Checking SDRAM Data Width
n/a / x8
Minimum Clock Delay from Back to Back
Random Column Address
t
ccd = 1 CLK
16
17
18
19
20
21
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
1, 2, 4, 8
4
0F
04
06
01
01
00
0F
04
06
01
01
00
0F
04
06
01
01
00
CL = 2 & 3
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
Non Buffered/Non
Reg.
22
23
24
25
26
27
28
29
SDRAM Device Attributes: General
Vcc tol ± 10%
7.5 ns/10.0 ns
5.4 ns/6.0 ns
Not Supported
0E
75
54
00
00
0F
0E
0F
0E
A0
60
00
00
14
0F
14
0E
A0
60
00
00
14
0F
14
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1 Not Supported
Minimum Row Precharge Time tRP
15 ns/20 ns
14 ns/15 ns
15 ns/20 ns
Minimum Row Active to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
V436516Y04V Rev. 1.0 October 2001
4
MOSEL [ MOSEL VITELIC, CORP ]
