Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~16
ta(A)
tv (A)
ta (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tdis (S1)
tdis (S2)
ta (S2)
ta (OE)
ten (OE)
OE
(Note 3)
tdis (OE)
(Note 3)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~16
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tsu (S2)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
W
tdis (W)
ten(OE)
ten (W)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
5