SP8853A/B
An F1 or F2 update cycle will consist of a byte containing
24 bits whereas the reference byte will contain 18 bits. The
device requires 3 bytes, each with a chip select sequence,
totalling 66 bits to fully program.
When the dual modulus A counter is set to 48/9, the data
required to set the counter is reduced by one bit, leaving an
unused bit in the 22-bit F1/F2 buffer. This bit must always be
set to zero when the 48/9 mode is required. Various
programming sequences are shown in Fig. 7.
The data entry and storage registers are always powered
up, making it possible to enter data when the device is in the
powered down state.
PD2
PD2
Result
0
0
FREF and FPD outputs off, charge pumps 1 and 2 on
1
0
1
0
1
1
FREF and FPD outputs on, charge pump 1 off, charge pump 2 on
FREF and FPD outputs off, charge pump 1 disabled by lock detect, charge pump 2 on
FREF and FPD outputs on, charge pump 1 disabled by lock detect, charge pump 2 on
Table 4
F
REF
F
15V
15V
15V
PD
LOOP FILTER
C2
C1
Rx
Rx
2·2k
R2
15V
−
+
0·25
Rb
RPD
Rb >
SL562
PD2 current
4
3
2
1
28 27 26
5
25
24
23
22
21
20
19
V
CC
2
6
7
15V
8
SP8853
9
33p
10
11
39p
1n
VOLTAGE
CONTROLLED
OSCILLATOR
12 13 14 15 16 17 18
0·1µ
1n
CONTROL
MICRO
1n
Fig. 6a Typical application
V
V
VARICAP
SUPPLY
CC
CC
15V
TO LOOP
AMPLIFIER
FROM
CHARGE
PUMP
Cd
10k
Ra
Ra
21
20
19
NC
TO VCO
3
2
1
28 27 26
EXTERNAL
REFERENCE
SOURCE
25
24
470
LOOP
FILTER
SP8853
22k
0·25
PD2 current
Ra > 23
Fig. 6b Connection
of external reference
Fig. 6c Use of lock detect circuit with PD1
Fig. 6d Simple discrete amplifier
Fig. 6 Application diagrams
6
MITEL [ MITEL NETWORKS CORPORATION ]
