SP8853A/B
10
RF INPUT
f
PD
16/17 OR 8/9
CONTROL
A COUNT
1LOGIC
M COUNT
1LOGIC
11
RF INPUT
PHASE
DETECTOR
DUAL
F1/F2
LOGIC
4 BIT
15 BIT
2 BIT
1 BIT
DATA
CHARGE
PUMP 1
3
13
BUFFER
PD1
F1/F2
14
DATA
N0
N0
N3
N4
N18
N19
N20
N21
15
DATA
INPUT
2-BIT
SR
CLOCK
22 BIT SHIFT REGISTER
24
28
RPD
Cd
16
ENABLE
N12
N13
N14
N15
CHARGE 25
POWER
DOWN
6
PD2
PUMP 2
SINGLE
REFERENCE
BUFFER
27
LOCK
DETECT
13 BIT
1 BIT
2 BIT
5
F
F
*
REF
OUTPUT
LOGIC
INTERFACE
4
R
*
PD
COUNT
f
REF
REFERENCE
DIVIDER
*F
and F
outputs are reversed by the phase detector
REF
PD
sense bit in the F1/F2 programming word. The pin allocations
shown are correct when the sense bit is low (see Table 2 and Fig. 7).
21
CRYSTAL
20
Fig. 2 SP8853 block diagram
V
PD1
CC
3
Output current at pin 27 is proportional to
voltage difference between pins 25 and 28,
45k
10k
CHARGE PUMP 1 DISABLE
(SEE TABLE 4)
I
MAX = 625µA
CHARGE
PUMP 1
−
+
−
31
+
CHARGE
PUMP 2
31
TRANSCONDUCTANCE
AMPLIFIER
−
+
27
31 BUFFER
LOCK DETECT
f
PD
PHASE
DETECTOR
DUAL VOLTAGE
COMPARATOR
f
REF
45k
24
25
PD2
28
RPD
Cd
Fig. 3 Detailed block diagram of lock detect circuit
2
MITEL [ MITEL NETWORKS CORPORATION ]
