SP8853A/B
DESCRIPTION
Prescaler and AM Counter
The programmable divider chain is of AM counter design
and therefore contains a dual modulus front end prescaler, an
A counter which controls the dual modulus ratio and an M
counter which controls the bulk multi-modulus division.
A programmable divider of this type has a division ratio of
MN1A and a minimum integer steppable division ratio
of N(N21).
In the SP8853, the dual modulus front end prescaler is a
dual N ratio device, capable of being statically switched
between 416/17 and 48/9 ratios. The controlling A counter is
of four-bit design, allowing a maximum count sequence of 15
(2421), which begins with the start of the M counter sequence
and stops when it has counted by the pre-loaded number of
cycles. While the A counter is counting, the dual modulus
prescaler is held in the N11 mode then reverts to the N mode
at the completion of the sequence.
The M counter is a 15-bit asynchronous divider which
counts with a ratio set by a control word. In both A and M
counters the controlling data from the F1/F2 buffer is loaded
in sequence with every M count cycle. The N ratio of the dual
modulus prescaler is selected by a one-bit word in the
reference divider buffer and, when when a ratio of 48/9 is
selected, the A counter requires only three programming bits,
having an impact on the frequency bit allocation as described
in the data entry section.
F1 or F2 word
Charge pump 1
current (µA)
Charge pump 2
multiplier
G2
G1
0
1
0
1
0
0
1
1
50
75
125
200
1
1·5
2·5
4
Table 1 Charge pump currents
Output for RF phase lag
F1/F2 sense bit
Pins 3 and 25
Pin 4
Pin 5
0
1
Current source
Current sink
FPD
FREF
FREF
FPD
Table 2
Data Entry and Storage
The data section of the SP8853 consists of a data input
interface, a data shift register and three data buffers.
Data is entered to the data input interface via a three-wire
highway, with DATA (pin 24), CLOCK (pin 15) and ENABLE
(pin16) inputs. The input interface routes the data into a 24-
bit shift register with bus connections to three data buffers.
Dataenteredviatheserialbusistransferredtotheappropriate
data buffer on the negative transition of the data enable input
according to the two final data bits C1 and C2 as shown in
Table 3. The MSB of the data is entered first.
Reference Source and Divider
The reference source in the SP8853 is obtained from an
on-chip oscillator which is frequency controlled by an external
crystal. The oscillator can also function as a buffer amplifier to
allowtheuseofanexternalreferencesource. Inthismode, the
source is simply AC-coupled into the oscillator transistor base
on pin 20.
2-bit SR contents
Buffer loaded
C2
C1
Theoscillatoroutputiscoupledtoaprogrammablereference
counter (R) whose output is the reference for the phase
detector. The reference divider is a fully programmable 13-bit
asynchronous design and can be set to any division ratio
between 1 and 8191. The actual division ratio is controlled by
a data word stored in the internal reference buffer.
0
1
0
0
0
1
F1
F2
Transfer A counter bits (N0:N3)
into 4-bit buffer (see Figs. 2 and 7)
1
1
Reference
Table 3
Phase Detector
The SP8853 contains a digital phase detector which feeds
two charge pump circuits. Charge pump 1 has preset currents
which are programmble as shown in Table 1. Charge pump 2
has a current level set by an external resistor RPD; the current
is multiplied by a factor which is determined by bits G1 and G2
of the F1 or F2 word (see Table 1). Note that charge pump 2
current is pin 24 current 3 muliplication factor, where
The dual F1/F2 buffer can receive two 22-bit words and
controls the programmable divider A and M counters using 19
bits, the phase detector gain with two bits and the phase
detector sense with one bit. A fourth input from the synthesiser
control system selects the active buffer.
The third buffer contains only 16 bits, 13 being used to set
the reference divider division ratio and 2 to control the phase
detector enable logic. The remaining bit sets the dual modulus
prescaler N ratio.
V
CC21·5V
RPD
I pin 24 =
A lock detect circuit is connected to the output of charge
pump 2. when the voltage level at pin 25 is between
approximately 2·25V and 2·75V, LOCK DETECT (pin 27) will
be low and charge pump 1 disabled, depending on the PD1
and PD2 programming bits as shown in Table 4.
TheoutputsignalsfromtheR andM countersareavailable
on pins 4 and 5 (FPD and FREF) when programmed by the
reference programming word; the various options are shown
in Table 4. An external phase detector may be connected to
pins 4 and 5 and may be used independently or in conjunction
with the on-chip phase detector.
The data words may be entered in any individual multiple
sequence and the shift register can be updated whils the data
buffers retain control of the synthesiser with the previously
loaded data. This enables four unique data words to be stored
in the device, with three in the data buffers and a fourth in the
shift register, while the chip is enabled. The F1 word may also
be updated while F2 is controlling the programmable divider
and vice-versa.
The dual F1/F2 buffer enables allows the device to be
toggled between two frequencies using the F1/F2 select input
at a rate determined by the comparison frequency and also
permits random frequency hopping at a rate determined by a
btye load period; this is possible because the loop can be
locked to F1 while F2 is updated by entering new data via the
shift register. The F1/F2 input is high to select F1.
To allow for control direction changes introduced by the
designofthecontrolloop,acontrolbitintheF1/F2programming
word interchanges the inputs to the on-chip phase detector
and reverses the functions on pins 4 and 5 (see Table 2).
5
MITEL [ MITEL NETWORKS CORPORATION ]
