SP8853A/B
PHASE
DETECTOR GAIN
CONTROL
(SEE TABLE 1)
MSB
LSB
G2 G1 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 C2 C1
15-BIT PROGRAMMABLE COUNTER (M COUNTER)
4-BIT
CONTROL
LOGIC
PROGRAMMABLE
COUNTER
PHASE
DETECTOR
SENSE BIT
(SEE TABLE 2)
(SEE
(A COUNTER)
TABLE 3)
Fig. 7a F1 or F2 word, bit allocation with 416/17 selected
PHASE
DETECTOR GAIN
CONTROL
(SEE TABLE 1)
MUST BE ZERO
MSB
LSB
G2 G1 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23
0
22 21 20 C2 C1
15-BIT PROGRAMMABLE COUNTER (M COUNTER)
3-BIT
PROGRAMMABLE LOGIC
COUNTER (SEE
(A COUNTER) TABLE 3)
CONTROL
PHASE
DETECTOR
SENSE BIT
(SEE TABLE 2)
Fig. 7b F1 or F2 word, bit allocation with 48/9 selected
DUAL MODULUS
N RATIO SELECT
0 = 416/17
1 = 48/9
MSB
LSB
212 211 210 29 28 27 26 25 24 23 22 21 20 C2 C1
PD1 PD2
CONTROL
LOGIC
PHASE
DETECTOR
BISTABLE
13-BIT PROGRAMMABLE COUNTER (R COUNTER)
(SEE
TABLE 3)
CONTROL
(SEE TABLE 4)
Fig. 7c Reference word bit allocation
F1 WORD
22 BITS
F2 WORD
REF WORD
0
0
22 BITS
1
0
22 BITS
1 1
DATA
22 CLOCKS
22 CLOCKS
22 CLOCKS
DATA CLOCK
CHIP SELECT
DATA LOADS ON FALLING EDGES
Fig. 7d Data load sequence
Fig. 7 Data format diagrams
7
MITEL [ MITEL NETWORKS CORPORATION ]
