Preliminary Information
MT93L16
Address:
3Ah Read
Receive (Rout) Peak Detect Register 1 (ROPD1)
7
6
5
4
3
2
1
0
Power Up
Reset 00h
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
1
0
4
6
5
7
3
2
MSB
LSB
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
0
1
2
3
4
5
6
7
These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see
Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.
Address:
3Bh Read
Receive (Rout) Peak Detect Register 2 (ROPD2)
7
6
5
4
3
2
1
0
Power Up
Reset 00h
ROPD
ROPD
ROPD
8
ROPD
ROPD
ROPD
ROPD
ROPD
10
11
9
12
15
14
13
MSB
LSB
ROPD
ROPD
8
9
ROPD
ROPD
ROPD
ROPD
ROPD
ROPD
10
11
12
13
14
15
See Above description
Address:
36h Read
Send (Sin) Peak Detect Register 1 (SIPD1)
7
6
5
4
3
2
1
0
Power Up
Reset 00h
SIPD
SIPD
SIPD
3
SIPD
SIPD
SIPD
0
SIPD
5
SIPD
1
4
6
2
7
MSB
LSB
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
0
1
2
3
4
5
6
7
These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see
Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.
Address:
37h Read
Send (Sin) Peak Detect Register 2 (SIPD2)
7
6
5
4
3
2
1
0
Power Up
Reset 00h
SIPD
SIPD
SIPD
11
SIPD
SIPD
SIPD
8
SIPD
13
SIPD
9
12
14
10
15
MSB
LSB
SIPD
SIPD
8
9
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
10
11
12
13
14
15
See above description
21
MITEL [ MITEL NETWORKS CORPORATION ]
