MT93L16
Preliminary Information
COMMAND/ADDRESS
DATA INPUT/OUTPUT
DATA 1
R/W
A
0
A
1
A
2
A
3
A
4
A
5
X
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SCLK
CS
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16.
The MT93L16: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 8 - Serial Microport Timing for Intel Mode 0
COMMAND/ADDRESS
DATA INPUT
DATA 2
Receive
R/W A
5
A
4
A
3
A
2
A
1
A
0
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA OUTPUT
DATA 1
Transmit
High Impedance
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SCLK
CS
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16.
The MT93L16: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire
12
MITEL [ MITEL NETWORKS CORPORATION ]
