MT93L16
Preliminary Information
Bit 7
Bit 6
(O)
Sout/Rout
V
CT
tASHZ
tDSD
tC4H
VH
VL
(I)
C4i
V
CT
tF0iS tF0iH
tC4L
VH
VL
(I)
F0i
V
CT
tDSS tDSH
start of frame
VH
VL
(I)
Rin/Sin
V
CT
Bit 6
Bit 7
Figure 11 -GCI Data Port Timing
)
Bit 7
Bit 6
(O)
Sout/Rout
V
CT
tDSD
tC4H
tASHZ
VH
VL
(I)
C4i
V
CT
tF0iS tF0iH
tC4L
VH
VL
(I)
F0i
V
CT
start of frame
tDSS tDSH
VH
VL
(I)
Rin/Sin
V
CT
Bit 6
Bit 7
Figure 12 - ST-BUS Data Port Timing
Bit 7
Bit 6
Bit 5
(O)
V
Sout/Rout
CT
tAHZ
tSD
tDD
tBCH
VH
VL
(I)
V
BCLK
CT
tSSS
tBCP
tBCL
tSSH
VH
VL
(I)
ENA1
V
CT
or
(I)
ENA2
tDIS
tDIH
start of frame
VH
VL
(1)
V
CT
Rin/Sin
Bit 7
Bit 6
Bit 5
Notes: O. CMOS output
I. CMOS input (5V tolerant)
(see Table 8 for symbol definitions)
Figure 13 - SSI Data Port Timing
16
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